The present invention relates to electronic circuits, and more particularly, to configurable buffer circuits and methods.
FIG. 1 illustrates a prior art current mode logic (CML) buffer circuit 100 that is used in a transmitter circuit. CML buffer circuit 100 includes constant current source circuit 101, switch circuits 102-103, and resistors 104-105. CML buffer circuit 100 is coupled between a node at a supply voltage VCC and a node at a low voltage VSS (e.g., ground).
CML buffer circuit 100 buffers a differential input signal VIN to generate a differential output signal VOUT. The differential input signal VIN is based on input voltage signals IN and INB (i.e., VIN=IN−INB). The differential output signal VOUT is based on output voltage signals VOP and VON (i.e., VOUT=VOP−VON). The conductive states of switch circuits 102-103 are controlled by input voltage signals IN and INB, respectively. Input voltage signal INB is the logical inverse of input voltage signal IN. The voltage range for both of signals IN and INB is from voltage VSS to voltage VH, where VH is the voltage of the node between switch circuits 102 and 103. CML buffer circuit 100 generates output voltage signal VOP between switch circuit 102 and resistor 104. CML buffer circuit 100 generates output voltage signal VON between switch circuit 103 and resistor 105.
When input voltage signal IN is in a logic high state, switch circuit 102 is closed, input voltage signal INB is in a logic low state causing switch circuit 103 to be open, and the current I1 from current source circuit 101 flows through switch circuit 102. Differential output signal VOUT equals I1×R1, where R1 equals the resistance of each of resistors 104-105.
When input voltage signal IN is in a logic low state, switch circuit 102 is open, input voltage signal INB is in a logic high state causing switch circuit 103 to be closed, and the current I1 from current source circuit 101 flows through switch circuit 103. Differential output signal OUT equals −I1×R1.
The common mode voltage VCM of CML buffer circuit 100 equals (I1×R1)/2. The peak-to-peak differential voltage swing of the differential output signal VOUT equals 2×I1×R1.
FIG. 2 illustrates a prior art H-bridge buffer circuit 200 that is used in a transmitter circuit. H-bridge buffer circuit 200 includes constant current sources 201-202, switch circuits 203-206, and resistors 207-208. H-bridge buffer circuit 200 is coupled between a node at a supply voltage VCC and a node at a low voltage VSS.
H-bridge buffer circuit 200 buffers a differential input signal VIN to generate a differential output signal VOUT. The differential input signal VIN is based on input voltage signals IN and INB (i.e., VIN=IN−INB). The differential output signal VOUT is based on output voltage signals VOP and VON (i.e., VOUT=VOP−VON). The conductive states of switch circuits 203 and 206 are controlled by input voltage signal IN, and the conductive states of switch circuits 204-205 are controlled by input voltage signal INB. Input voltage signal INB is the logic inverse of input voltage signal IN. H-bridge buffer circuit 200 generates output voltage signal VOP between switch circuits 203-204. H-bridge buffer circuit 200 generates output voltage signal VON between switch circuits 205-206.
H-bridge buffer circuit 200 also includes a circuit such as an amplifier (not shown) that generates a constant voltage VCM between resistors 207-208. Voltage VCM equals the common mode voltage of output voltage signals VOP and VON.
When input voltage signal IN is in a logic high state, switch circuits 203 and 206 are closed, input voltage signal INB is in a logic low state causing switch circuits 204-205 to be open, and the current I2 from current source 201 flows through switch circuit 203, resistors 207-208, switch circuit 206, and current source 202. Differential output signal VOUT equals I2×2×R2, where R2 equals the resistance of each of resistors 207-208.
When input voltage signal IN is in a logic low state, switch circuits 203 and 206 are open, input voltage signal INB is in a logic high state causing switch circuits 204-205 to be closed, and the current I2 from current source 201 flows through switch circuit 205, resistors 208 and 207, switch circuit 204, and current source 202. Differential output signal VOUT equals −I2×2×R2.
H-bridge buffer circuit 200 generates a peak-to-peak differential voltage swing in VOUT that equals 4×I2×R2. If R1 equals R2, then H-bridge buffer circuit 200 draws half as much current as CML buffer circuit 100 to achieve the same output voltage swing in VOUT (i.e., I1=2×I2). As a result, H-bridge buffer circuit 200 consumes less power than CML buffer circuit 100.
However, H-bridge buffer circuit 200 generates a more limited range in the common mode voltage VCM of the differential output signal VOUT than CML buffer circuit 100. The common mode voltage VCM of the differential output signal VOUT of H-bridge buffer circuit 200 is limited based on the equation VCM≧(I2×R2)+VL+VSW2, where VL is the voltage of the node between switch circuits 204 and 206, and VSW2 is the voltage drop across switch circuit 204 or 206.
H-bridge buffer circuit 200 has less voltage headroom between supply voltage VCC and low voltage VSS compared to CML buffer circuit 100, because H-bridge buffer circuit 200 includes two current source circuits 201-202 that each consume a portion of the voltage drop between VCC and VSS. In addition, H-bridge buffer circuit 200 has a higher output capacitance than CML buffer circuit 100 at the nodes that generate output voltage signals VOP and VON. The higher output capacitance in H-bridge buffer circuit 200 slows down transitions in output voltage signals VOP and VON. H-bridge buffer circuit 200 generates more symmetrical waveforms in output voltage signals VOP and VON than CML buffer circuit 100.